1. Field of the Invention
This invention is in the field of digital logic circuitry, and more particularly relates to an improved one's complement adder.
2. Description of the Prior Art
Conventional binary adders for adding two binary numbers, A.sub.i, B.sub.i each of i bits, where i is an integer other than 0, are well known in the art. An example of such circuit that can be used to add two binary numbers is that illustrated and described in U.S. Pat. No. 4,084,252 which issued on Apr. 11, 1978 and is assigned to Honeywell Information Systems Inc., the assignee of this Application. Such an adder can be made into a one's complement adder by connecting the most significant carry-out signal, that present at the carry-out terminal, to the least significant carry-in line, the carry-in terminal of the adder.
Modulo 2.sup.i -1 addition, or the one's complement system, is a commonly required function in error detection circuitry for arithmetic operations of some digital data processing systems. Expressed mathematically, A.sub.i is an i bit one's complement number which is an input to the adder; and B.sub.i is an i bit one's complement number which is a second input to the adder. F.sub.i is the i bit output of the adder; and EQU F.sub.i =A.sub.i +B.sub.i
Until recently it was thought that a multi-bit one's complement adder would when the sum of F.sub.i =zero of A.sub.i and B.sub.i was produced, that the adder would produce F.sub.i as a positive zero, 0,0--00 instead of a negative zero 1,1,--1, as stated in a paper: Shedletsky, John J. Comments on the Sequential and Indeterminant Behavior of an End-Around-Carry Adder IEEE Transactions on Computers, March, 1979, p. 270-271 that the sum of a number and its one's complement, or when F.sub.i =zero, that zero may be positive or negative depending on the preceeding state of the adder and the relative propagation delays in the adder. Shedletsky, in his paper, shows that the choice between the two possible zero states, all zeroes or all ones, can depend on the preceeding values of the carry lines, sequential behavior; or on the relative propagation delays in the adder, indeterminate behavior, which is also known as a race condition.
Shedletsky proposes a solution to the problem; namely by providing additional circuitry to drive all the carry lines to the one state when the sum of A.sub.i and B.sub.i is zero in the one's complement system.